1. Field of the Invention
Embodiments of the present invention relate to a semiconductor integrated circuit having a so-called MTCMOS (multi-threshold complementary metal oxide semiconductor)-based and non-MTCMOS-based circuit cells in a mixed manner in the same circuit block.
2. Description of the Related Art
Controlling the supply and interruption of the source or reference voltage to the circuit cells is known, for example, as a circuit technique called MTCMOS (multi-threshold complementary metal oxide semiconductor). For instance, MTCMOS connects a power switch transistor having a higher threshold voltage than the transistors of the functional circuit to the path adapted to supply the source or reference voltage (e.g., GND voltage) to each of the circuit blocks serving a specific function. When a circuit block is not used, the power switch transistor is turned off, interrupting the leak current to the transistors in the circuit block. This ensures significantly reduced wasteful leak current flowing into the unused circuit block.
A semiconductor integrated circuit has already been proposed in which the power switch transistors in a cell form are laid out as appropriate in the circuit cell layout region. This semiconductor integrated circuit is intended to eliminate the inconvenience of manually laying out the power switch transistors in the design of a semiconductor integrated circuit including MTCMOS-based circuit blocks (refer to Japanese Patent Laid-Open No. 2005-259879, hereinafter referred to as Patent Document 1).
MTCMOS-based and non-MTCMOS-based circuit cells are laid out in a mixed manner in the circuit block described in Patent Document 1.